interfaces, crypto

Features
Includes ST state-of-the-art patented
technology
Core
32-bit Arm Cortex-M7 core with doubleprecision FPU and L1 cache: 16 Kbytes of data
and 16 Kbytes of instruction cache; frequency
up to 480 MHz, MPU, 1027 DMIPS/
2.14 DMIPS/MHz (Dhrystone 2.1), and DSP
instructions
Memories
128 Kbytes of flash memory
1 Mbyte of RAM: 192 Kbytes of TCM RAM (inc.
64 Kbytes of ITCM RAM + 128 Kbytes of
DTCM RAM for time critical routines),
864 Kbytes of user SRAM, and 4 Kbytes of
SRAM in Backup domain
Dual mode Quad-SPI memory interface
running up to 133 MHz
Flexible external memory controller with up to
32-bit data bus:
SRAM, PSRAM, NOR flash memory
clocked up to 133 MHz in synchronous
mode
SDRAM/LPSDR SDRAM
8/16-bit NAND flash memories
CRC calculation unit
Security
ROP, PC-ROP, active tamper, secure firmware
upgrade support, Secure access mode
General-purpose input/outputs
Up to 168 I/O ports with interrupt capability